A blog about space computing.

Author: Fabio Malatesta

  • Accelerating RISC-V Processor Verification: A Co-Simulation Strategy

    Accelerating RISC-V Processor Verification: A Co-Simulation Strategy

    With RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through rigorous verification becomes more crucial than ever.  We have embraced a robust co-simulation strategy for verifying the NOEL-V RISC-V processor. This strategy integrates behavioural simulation with the SPIKE open-source RISC-V ISA simulator. The NOEL-V is a synthesizable VHDL model of a…

  • Integrating SpaceWire and SpaceFibre for Space Communication

    Integrating SpaceWire and SpaceFibre for Space Communication

    We have introduced a system that bridges between SpaceWire and SpaceFibre links, providing a robust, high-speed communication solution for space applications. This innovation leverages our SpaceWire router IP core and SpaceFibre interface IP core, ensuring data transmission between the two protocols without the need for software intervention. Understanding SpaceWire SpaceWire is a well-established data communication…

  • Addressing Challenges with FPGAs in Space Using the GR716B Microcontroller

    Addressing Challenges with FPGAs in Space Using the GR716B Microcontroller

    In the realm of space electronics, reliability is paramount. Every component onboard a spacecraft must withstand the harsh conditions of outer space, including extreme temperatures, vacuum, and radiation. Among these components, Field-Programmable Gate Arrays (FPGAs) play a crucial role and come with their own set of challenges. Challenges with FPGAs in Space Two significant challenges…

  • A Striped Bus Architecture for Minimizing Multi-Core Interference

    A Striped Bus Architecture for Minimizing Multi-Core Interference

    Understanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture might seem straightforward, the landscape becomes notably more complex when dealing with multiple cores. Here, contention for shared resources such as caches, buses, and peripherals add layers of uncertainty to…

  • How to Design a RISC-V Space Microprocessor

    How to Design a RISC-V Space Microprocessor

    In the world of advanced technology and exploration, some missions take us where ordinary microprocessors cannot dare to go. Whether exploring the depths of space or operating in avionics, the presence of intense radiation poses a grave threat to electronic components. To overcome this challenge, engineers have devised a solution: radiation-hardening. Radiation-hardened – or rad-hard…